Following Moure Law

Intel presents fully functional chips SRAM made using 65 nm technlogy.

Intel prepares to start production of microchips using 65 nm technology for 300 mm silicon surfaces. They promise a further increase of computing performance and decrease of leaks. At the end of the August the corporation presents fully functional SRAM chips, produced by new technology and containing about half of a billion transistors.

Mark Bor, director of Process Integration and Architecture division in Intel's Technology and Manufacturing group, have said that transition to 65 nm chip design does not lead to revolutionary changes in production process. In particular, they continue to use a technology of strained silicon with the same materials which are used now for 90 nm chip production, i. e. silicium-germanium hybrid and silicium nitride for transistors of p- and n- types, and dielectrics with carbonic additions with low-k coefficient. Intel representatives said that both of these principles of technological process were improved.

However Bor rejected to said in detail which improvements were implemented, just confirmed some guesses, for example, that artificially created strains in a silicon structure become stronger. Among the new things one mentions the increase of number of copper surfaces from seven to eight, and sleep transistors which switch off a power of a separate chip blocks when they are not used.

Following Moure law they at Intel again decrease a size of a transistor and increase their density on a cristal. The channel width is decreased down to 35 nm from 50 nm in 90 nm technology, and the width of surface if dielectric lock (dioxide of carbon) remains the same. This according to Bor allows to prevent a leak increase. When migrating to 45 nm design (2007) at Intel they are going to decrease a channel width up to 25 nm and start using some “material with high-k” instead of dioxide of carbon. They also plan to replace polycrystall locks with metal locks. Speaking more precisely they will use some metal combination. What is ment besides these things is hidden by silence in the corporation.

Intel plans to produce 45 nm microchips on three factories. One of them, the factory at Hilsboro in Oregon state, becomes a training ground for the new technology.